This IEEE Philadelphia Section Hands-On Workshop will introduce students and professionals to modern embedded processing systems using the field programmable gate array (FPGA).

A field-programmable gate array is a semiconductor device containing programmable logic components or "logic blocks", and programmable interconnects. In an FPGA, logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.  Logic blocks and interconnects of traditional FPGAs can be combined with hard core microprocessor, such as a PowerPC, to form a complete system on a programmable chip, or alternatively with soft programmable cores, which is a processor built with programmable logic. FPGAs have found applications in digital signal processing, speech recognition, software-defined radio, aerospace and defense systems, medical imaging, computer vision, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas.

This new paradigm in embedded design utilizes the Verilog hardware description language (HDL) method of synthesizing the controller and datapaths,  the Finite State Machine (FSM), as well as external interface hard core peripherals, custom internal soft core  peripherals and the soft core processor.

This Hands-On Workshop features the Xilinx Spartan-3E FPGA evaluation hardware, the Xilinx Integrated Synthesis Environment (ISE) electronic design automation (EDA) software tool in the Verilog HDL, the Xilinx CORE Generator for LogiCORE blocks and the auxiliary EDA software for the Xilinx 8-bit PicoBlaze and 32-bit MicroBlaze soft core processor.

The participants will have a hands-on opportunity to investigate the development of embedded systems using the Xilinx Spartan-3E FPGA hardware evaluation board.  The supplementary text described below and optional Spartan-3E FPGA hardware evaluation boards provides support for continuing professional education after the conclusion of the Workshop.

Presenter:  Dennis Silage is a Professor in the Department of Electrical and Computer Engineering at Temple University .  He has a Ph.D. in Electrical Engineering from the University of Pennsylvania . He is a senior member of the IEEE and director of the System Chip Design Center www.temple.edu/scdc, which researches the application of the Xilinx FPGA in digital signal processing and digital communication.

Topics:        Programmable Logic Devices
                        Hardware Description Languages
                        Behavioral Models in Verilog
                        Finite State Machines
                        Controller-Datapath Construct
                        C to Verilog Translation

                        Xilinx ISE WebPACK
                        Xilinx CORE Generator
                        Xilinx Architecture Wizard
                        Xilinx LogiCORE Blocks

                       Spartan-3E Starter Board                           

                        DSP Embedded System
                        FIR Compiler LogiCORE Block
                        Sine-Cosine Look-Up Table LogiCORE Block
                        DDS Compiler LogiCORE Block

                        Xilinx PicoBlaze Development Tools
                        Xilinx PicoBlaze Processor Architecture
                        Xilinx PicoBlaze Reference Project
                        Xilinx MicroBlaze Development Tools
                        Xilinx MicroBlaze processor Architecture

Text:  Dennis Silage, Embedded Design Using Programmable Gate Arrays, Bookstand Publishing, 2008, ISBN 978-1-58909-486-4, soft cover, 320 pages with archived project files (included with registration) www.bookstandpublishing.com/m/dennissilage

Registration :  IEEE Members $425 before September 19th; $450 after September 19th.  Non-members $475 before September 19th; $500 after September 19th. Registration includes book and parking. Lunch is not included, but is available nearby.

To Register:  http://www.ieeephiladelphia.org/   then 'Register for a Meeting' (note that the second date October 25th is incorrect and should be Friday October 24th)

Background Required:  Knowledge of combination and sequential digital logic concepts and a conversational computer programming language (such as C).

Intended Audience:  Practicing Electrical Engineers, Computer Engineers and other professionals without substantial hands-on experience with the Verilog HDL in embedded design using programmable gate arrays.

Location:  College of Engineering , Temple University , 12th and Norris Streets, Philadelphia .  Parking which is included is availability immediately adjacent to the College.

Optional Hardware and Software:  Xilinx Spartan-3E Starter Board, www.digilentinc.com ($150), Xilinx ISE WebPACK (freely downloadable) www.xilinx.com

Additional information: silage@temple.edu